1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to an SOI (silicon on insulator) MOSFET.
2. Discussion of the Related Art
A CMOS/SOI device is used to reduce parasitic capacitance, have an abrupt slope of threshold voltage, prevent short channel effect, and remove latchup of CMOS. However, this CMOS/SOI has some problems. The most significant problem is how to prevent parasitic capacitance in a floated body NMOSFET.
As collision ionization constant of holes is very low in a PMOSEET in comparison to an NMOSEET, the problem of parasitic capacitance is not so serious as in the NMOSFET. Recently research and development has been directed to how to prevent parasitic capacitance.
A conventional semiconductor and a conventional method for fabricating the same will be described with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view showing a structure of a conventional semiconductor device, including a substrate 21 in which a buried insulating layer 23 is formed, device isolating layers 27 under the surface of the substrate 21, a gate electrode 31a formed on the substrate 21 of an active region between the device isolating layers 27, and source/drain regions 35/35a formed beneath the surface of the substrate 21 at both sides of the gate electrode 31a.
The substrate 21 is of a p type of high resistance. The source/drain regions 35/35a are of an n type that is opposite to that of the substrate 21.
A method for fabricating the above described semiconductor substrate will be described with reference to the accompanying drawings.
FIGS. 2A to 2E are cross-sectional views showing process steps of a method for fabricating a semiconductor device.
Referring initially to FIG. 2A, a buried insulating layer 23 is formed in a p type semiconductor substrate 21. The buried insulating layer 23 is 100 nm thick. The active substrate 21 is 50 nm thick.
Thereafter, the substrate 21 is etched by a predetermined depth with a photo etching process to form trenches 25.
Referring to FIG. 2B, an insulator is buried in the trenches so that device isolating films 27 are formed. Next, a channel ion implanting process is performed for adjusting threshold voltage.
Referring to FIG. 2C, a 50 Angstrom thick gate insulating film 29 is grown and a doped polysilicon layer 31 is formed. At the polysilicon layer is doped with n type impurity ions to form an NMOS device, and the polysilicon layer is doped with p type impurity ions to form a PMOS device.
Referring to FIG. 2D, the polysilicon layer 31 is selectively removed to form a gate electrode 31a and gate insulator 29. Next, an insulating layer made of an oxide or a nitride is deposited on the entire surfaces including the gate electrode 31a. The insulating layer is etched-back to form sidewall spacers 33 on both sides of the gate electrode 31a. With the sidewall spacers 33 and the gate electrode 31a serving as masks, impurity ions are implanted to form source/drain regions 35/35a beneath the surface of the substrate 31 at both sides of the gate electrode 31a.
Referring to FIG. 2E, the sidewall spacers 33 are removed. Next, Argon Ar ions are implanted to form damage layers 37 along impurity junction. At this time, the tilt angle for implanting the impurity ions is 4.about.70.degree. and the concentration of the ions is 2.times.10.sup.14 cm.sup.2.
R.sub.p is formed along the boundary of the substrate 21 and the buried insulating layer 23 due to the ion implanting process and damage layers may thus be formed by an ion implanting process.
Thereafter, an RTA (rapid thermal annealing) process is performed at a temperature of 950.degree. C. for 10 seconds.
A recombination center is formed in a parasitic bipolar transistor body in which source, body, and drain serve as emitter, base, and collector, respectively, thereby reducing the emitter injection efficiency.
Therefore, as for an NMOS, holes generated in a body easily go toward the source which acts as the emitter, so that deterioration of the floating body effect is prevented.
The conventional semiconductor device method for fabricating the same have the following problems. Since the damage generated at the boundary of a buried insulating layer and a substrate by an Ar ion implanting process affects a gate insulating layer, the reliability of the gate insulating layer becomes poor. Also the characteristic of hot carrier becomes poor since the damage is generated at the interface of the gate insulating layer. Further, the damage region is formed in source/drain regions, and the resistance of the source/drain is increased; thus reducing the current.